More and more electronic devices are equipped with semiconductor products including a microcomputer associated with an on board memory on the same semiconductor product, thus making up a real system on chip.
Increasing the power of such systems is done in particular by increasing the capacity of the Read Only Memories (ROM) that are used for storing the microprograms required to operate the integrated microcomputer.
However, increasing the capacity of ROMs poses serious problems for development teams.
For example, a first problem results from the increase in memory size that can currently reach 8, 16 or even 32 megabits, which makes memories extremely difficult to test with the traditional checking tools available to engineers. Indeed, a ROM is programmed by positioning a plate on the integrated circuit, with the plate comprising a set of contacts or vias for coding information to be stored in silicon.
FIG. 1 depicts the conventional operation of a memory cell or a memory point that comprises a transistor 1 serially connected with an element 2—a via or an open circuit—adapted to receive information to be coded. The unit is connected between ground (GND) and bit line 3 (BITLINE, that is in fact a column of the matrix), which line is in turn connected to the amplifiers (not shown) of the output stage of the memory.
Before any reading operation, the bit line is precharged to the supply voltage (Vdd). At the time of reading, address decoders (not shown) activate the gate of transistor 1 (carrying a signal WL or WORD LINE), making transistor 1 conductive and thus causing the bit line or column to be discharged when memory element 2 is a contact or a via. Such discharging is detected by a read amplifier (not shown) that thus outputs a logical “0”. In the opposite case, if element 2 is an open circuit—corresponding to a logical “1”—the bit line cannot be discharged and the information is then detected by the output amplifier.
It should be noted that when the pages that are stored in the memory—namely the lines of the matrix network forming the memory—have a majority of logical “0” positioned on the same bit, usually the opposite value is stored in the memory points present on that bit line for all the pages in the memory and an inverter is arranged at the output of the bit line or column in order to restore the correct information value. In this manner, a reduced number of vias in the memory points corresponding to the same bit lines can be ensured, which has the advantage of reducing the leakage currents that tend to spontaneously discharge the bit line and that tend to progressively increase as the size of components decreases.
FIG. 2 illustrates an example of a traditional architecture of a ROM, which is a 4-bit memory, with a 4-bit multiplexing rate. The ROM is based on a matrix network 21 associated with an address decoder 22 and control logic 23 generating all clock signals and the like that are required for its operation. Matrix network 21 comprises a number of rows corresponding to the number of pages that can be stored in memory, and a number of columns (BITLINE) 27-1 to 27-4, 28-1 to 28-4, 29-1 to 294 and 30-1 to 30-4, with each column corresponding to a bit line. A read system comprises an output stage 24.
Conventionally, to program the memory, the density, Pi, of “0” values that must be stored in 27-1, 27-2, 27-3 and 27-4 is determined and, if this density is higher than 50%, the values stored in all these columns are inverted. The procedure is the same for columns 28-1, 28-2, 28-3 and 28-4 and an inverter is provided for restoring the correct value of the stored information if the values are inverted.
This known mechanism makes it possible to reduce the leakage currents within the bit lines or columns. It is, however, not satisfactory. Indeed, it tends to create a considerable tangle among the columns forming the matrix network and, consequently, makes checking thereof very difficult.
It is noted that the increase in the ROM size involves a corresponding increase in the size of the plate and eventually, one ends up having to position and test several million, or even several tens of million, contacts and vias on the memory in order to ensure the integrity of the microprogram stored in the memory.
Traditional checking techniques and systems, in particular the ones based on Layout Versus Schematics (LVS), very quickly prove unable to run low level testing on a ROM of such size. Indeed, as the structure of the code to check cannot be hierarchically organized, it is necessary to “point-by-point” check the entirety of the code, i.e., by checking each memory cell, whether it is associated with a via or a contact, or not. This amounts to coding and processing a file or database containing several million bytes, which greatly exceeds the capacities of conventional checking devices.
Thus, it is then necessary to invest in newer, more powerful and more expensive check and test tools that will in turn become obsolete and insufficient when the size of ROM increases again.
To this major difficulty is added a second problem that results from the fact that the storage of some programs can lead to a great disparity of pattern densities, thus leading to important gradients within the matrix. Such occurrence of gradients proves to be cumbersome especially with the increasing miniaturization of patterns and it is desirable to be able to reduce the value of these gradients.
Furthermore, the presence of inverters in some bit lines introduces a third problem linked to the considerable access time within the memory, which also needs to be reduced.
Therefore, there is a need to completely reconsider the design of read only memories intended to be integrated in a semiconductor product, in order to solve the above-mentioned problems.